1. Field of the Invention
The invention relates to integrated MOS circuits and somewhat more particularly to a method of producing high packing density of integrated MOS circuits via silicon gate technology with self-adjusting contacts by using silicon nitride masking.
2. Prior Art
In the production of highly integrated semiconductor circuits, one of the more important goals is to pack as many circuit components (for example transistors) or, respectively, functional units per surface unit based on a controllable minimum size substrate. In achieving such goals, inactive regions of IC circuits (i.e., those regions which do not directly contribute to circuit function) are particularly bothersome. Such inactive regions include the non-usable regions at the peripheries of contact holes. These inactive regions are made-up by so-called safety clearances or spacings.
Presently, the production of MOS components perferably occurs via polysilicon technology. With this technology, the gate electrodes of field effect transistors as well as conductive paths or tracks for connecting such electrodes are composed of polysilicon. An essential advantage of this technique, in comparison to a technique where such electrodes and interconnections are composed of aluminum, is that interfering gate-source and gate-drain overlap capacitors can be kept very small and that with polysilicon an additional "interconnection level" is provided.
In instances of a n-channel as well as in instances of a p-channel silicon or, respectively, double-silicon-gate technology, contact holes must be produced on the SiO.sub.2 layers as well as on n.sup.+ - or p.sup.+ -doped monocrystalline silicon regions and on n.sup.+ - or p.sup.+ -doped polycrystalline silicon regions. In so doing, one must avoid having a portion of a contact hole surface projected over the region contacted because otherwise a danger exists that the metal interconnection applied over such contact hole surface may produce a short circuit to an adjacent p- or n-doped region of the monocrystalline silicon substrate. In instances where a projection of a contact hole surface extends over a polysilicon structure, besides a short circuit danger, there also exists a danger that as a result of an undercut (i.e., an under-etching) of the SiO.sub.2 layer beneath the polysilicon structure, an overhang of the polysilicon structure is produced, which can cause a break in the interconnection or path positioned over such overhang.
In order to prevent projections of contact holes (i.e., surfaces defining contact holes) over regions to be contacted, the so-called safety spacings are provided between the edges of a contact hole and the edges of adjacent doped silicon regions. These safety spacings are required because the spacing between two structure edges on two different structural planes cannot be arbitrarily exact but must only be within certain tolerances, which with the present state of the art is about .+-.2 .mu.m.
The prior art literature suggests various proposals for reducing and/or eliminating the above-described safety clearances or spacings about peripheries of contact holes.
German Offenlegungsschrift No. 27 23 374 suggests one such process wherein, with the aid of nitride layers, by use of their oxidation-inhibiting effects as well as their etch-stop effects, contact holes are produced so that the surface area thereof projects out over the polysilicon region to be contacted. This process requires an additional contact hole mask, and on the periphery of the resultant contact holes between the monocrystalline n.sup.+ - or p.sup.+ -doped regions and the metal interconnections, with this process as before, safety spacings must be provided and the contact hole sidewall slopes are very steep or even overhanging.
Another process (V. L. Rideout et al, "A One-Device Memory Cell Using A Single Layer Of Polysilicon And A Self-Registering Metal-To-Polysilicon Contact", International Electron Devices Meeting, Technical Digest, Washington, D.C., December 1977, page 258) suggests covering the polysilicon layer at those locations thereof where contact holes are to be formed with a double layer, a first layer of silicon dioxide and a second layer of silicon nitride, while the remaining surface areas of the desired polysilicon structures are masked with a silicon dioxide layer. Thereafter, the non-covered portions of the polysilicon layer are etched away. This method is similarly disadvantageous as the above-referenced DT-OS No. 27 23 374, with the difference being that the sidewall slopes of the polysilicon structures (rather than that of the contact holes) can be overhanging.
Another process is suggested by W. G. Oldham et al, "Improved Integrated Circuit Contact Geometry Using Local Oxidation", Electrochemical Society, Spring Meeting, Seattle, Wash., May 1978, page 690. In this process, the oxidation-inhibiting silicon nitride layer is applied after etching of the polysilicon layer. This nitride layer is etched in such a manner that it remains only over the surface areas where the contact holes are to be formed. A disadvantage of this method is that the side slopes of the polysilicon structures can be overhanging and in instances where contact holes are positioned entirely or partially on gate regions, the safety spacings to the above-described polysilicon structure edges are required.
A method which permits a decrease of the safety spacings at peripheries of contact holes between monocrystalline n.sup.+ -doped regions and metal interconnections or even an elimination thereof is suggested in German Offenlegungsschrift No. 25 09 315. In this method, after the contact holes are etched, doping material (such as phosphorous or arsenic) is applied into the contact holes. In this manner, a short circuit is prevented between the monocrystalline n.sup.+ -regions and the neighboring p-doped regions in instances of projecting contact holes. The safety spacings at the periphery of the contact holes to polysilicon structures are, however, still necessary with this method, now as before.